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![Header Image](docs/images/OISTER_Banner.jpg)
# OI!STER
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<img src="docs/images/OISTER-DIAG-30.png" width="750" height="750">
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The OI!STER is a purpose‑built STM32L5 target board that combines flexible power provisioning, comprehensive signal access, and dedicated interfaces for advanced debugging, glitching, and fault‑injection experiments. Power can be supplied through a USB‑C connector for laboratory use, a CR2032 coin cell mounted on the rear or an external voltage source, allowing seamless transition between bench‑top and field deployments without hardware modification.
All 48 pins of the QFP48‑package MCU are routed to dual 24‑pin headers located on the upper edge of the board, providing unobstructed access for external instrumentation and simplifying the wiring of custom test fixtures. Five debug headers expose standard SWD/JTAG signals, enabling integration with a wide range of open‑source debugging tools such as HydraBus and Black Magic Probe.
Six SMA connectors are organized into three functional pairs. One pair is wired to the external low‑speed crystal (LSE) input, a second pair to the high‑speed external crystal (HSE) input, and the third pair to the power‑rail node used for side‑channel analysis or ChipWhisperer‑style fault injection. Each SMA port can be electrically isolated by lifting a miniature jumper, a design decision that mirrors the rapid reconfiguration strategies recommended for hardware research platforms.
Additional solder jumpers are placed on the external‑clock traces and on each MCU power rail, allowing the user to short, disconnect, or reroute these nodes with a simple soldering operation. This feature accelerates experimental cycles by eliminating the need for PCB redesign when exploring alternative clock sources or power‑distribution topologies.
Overall, the OI!STER’s combination of features makes it a versatile foundation for reverse‑engineering, side‑channel, and fault‑injection investigations on the STM32L5 family.