unbinare/OISTER
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Updated Readme.md

Browse Source
This commit is contained in:
unbinare
2026-01-30 18:49:23 +01:00
parent 5cf1679725
commit 38e0dbd109
1 changed files with 27 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
README.md
View File

@@ -1,22 +1,40 @@
![Header Image](docs/images/OISTER_Banner.jpg)
<div align="center">
<img src="docs/images/OISTER-DIAG-30.png" style="max-width: 100%; height: auto";>
</div>
# OI!STER
<div align="center">
<img src="docs/images/OISTER-DIAG-30.png" width="750" height="750">
</div>
The OI!STER is a target board centered on salvaged STM32L5 microcontrollers (QFP48 package). It is engineered to support a wide range of hardware research activities, including advanced debugging, glitching, and fault-injection experiments. Power can be supplied via three interchangeable methods, enabling seamless transitions between laboratory benches and field deployments without any hardware modification. All 48 MCU pins are exposed through dual 24-pin headers on the board's upper edge, while additional debug, clock, and power-rail interfaces provide extensive configurability for custom test fixtures and side-channel analysis.
### Features
The OI!STER is a purpose‑built STM32L5 target board that combines flexible power provisioning, comprehensive signal access, and dedicated interfaces for advanced debugging, glitching, and fault‑injection experiments. Power can be supplied through a USB‑C connector for laboratory use, a CR2032 coin cell mounted on the rear or an external voltage source, allowing seamless transition between bench‑top and field deployments without hardware modification.
#### Flexible power provisioning
- USB-C connector for bench-top power.
- Rear-mounted CR2032 coin cell for portable operation.
- External voltage input for field deployments.
All 48 pins of the QFP48‑package MCU are routed to dual 24‑pin headers located on the upper edge of the board, providing unobstructed access for external instrumentation and simplifying the wiring of custom test fixtures. Five debug headers expose standard SWD/JTAG signals, enabling integration with a wide range of open‑source debugging tools such as HydraBus and Black Magic Probe.
#### Full MCU pin accessibility
- All 48 pins of the STM32L5 QFP48 MCU routed to two 24-pin headers on the upper edge, facilitating unobstructed connection of external instrumentation.
Six SMA connectors are organized into three functional pairs. One pair is wired to the external low‑speed crystal (LSE) input, a second pair to the high‑speed external crystal (HSE) input, and the third pair to the power‑rail node used for side‑channel analysis or ChipWhisperer‑style fault injection. Each SMA port can be electrically isolated by lifting a miniature jumper, a design decision that mirrors the rapid reconfiguration strategies recommended for hardware research platforms.
#### Debugging interfaces
- Five dedicated debug headers exposing standard SWD/JTAG signals.
- Compatibility with Open Source debugging tools such as HydraBus and Black Magic Probe.
Additional solder jumpers are placed on the external‑clock traces and on each MCU power rail, allowing the user to short, disconnect, or reroute these nodes with a simple soldering operation. This feature accelerates experimental cycles by eliminating the need for PCB redesign when exploring alternative clock sources or power‑distribution topologies.
Overall, the OI!STER’s combination of features makes it a versatile foundation for reverse‑engineering, side‑channel, and fault‑injection investigations on the STM32L5 family.
#### SMA connector suite (three functional pairs)
- Pair 1: Connected to the low-speed external crystal (LSE) input.
- Pair 2: Connected to the high-speed external crystal (HSE) input.
- Pair 3: Connected to a configurable power-rail node for side-channel or fault injection.
- Each SMA port can be electrically isolated by lifting a miniature jumper, allowing rapid reconfiguration.
#### Configurable clock and power rails
- Solder jumpers on external clock traces and on each MCU power rail.
- Eliminates the need for PCB redesign when experimenting with alternative clock sources or power-distribution topologies.
#### Research-oriented design
- Combines comprehensive signal access with modular power options, making the board a versatile foundation for reverse engineering, sidechannel analysis and fault-injection investigations targeting the STM32L5 family.
### Funding
This project received funding through [NGI0 Entrust](https://nlnet.nl/entrust), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) program. Learn more at the [NLnet project page](https://nlnet.nl/project/Unbinare-RET).